Kaiam develops and manufactures low-cost high-performance optical subassemblies, components, and transceivers – based on breakthrough hybrid Photonic Integrated Circuit (PIC) technology – for fiber optic communications applications.
As bandwidth needs outstrip the data rates of single electronic pipes, there is an increasing need for parallelism in data communications. For the shorter spans, parallel multi-mode ribbon fibers are used to carry multiple lanes of data. For longer spans, coarse wavelength division multiplexed (CWDM), and dense wavelength division multiplexed technologies (DWDM) are used in single mode fibers. At the longest lengths and in links where bandwidth efficiency is important, coherent architectures that enable multiple symbols per bit effectively combine multiple lanes onto the same wavelength of light.
These more complex parallel links require sophisticated packaging to meet the density requirements. Simply packaging a single laser in a TO can does not suffice. Currently, there are multiple solutions to increasing density, each with its own pros and cons:
- Monolithic integration of components onto a single InP substrate eliminates the coupling between the components, but is an expensive solution due to; the high cost of InP, yield impact of a relatively immature technology, and the performance trade-offs that must be met when combining different types of devices onto the same wafer. The development costs are huge, and unlike electronics, where integration leads to lower capacitance and higher speed, there is no performance advantage to integrated optics – merely savings in fiber handling. Monolithic integration on Silicon substrates is also problematic as silicon-based light sources tend to be inefficient and unreliable. In any kind of monolithic integration, high yields can be elusive as poor performance or burn-in on any individual component dooms the entire chip.
- Hybrid integration of individual components to form the equivalent of an electronic multi-chip module, has been the most studied approach. However, the very tight optical modes and extremely precise positioning needed for good coupling forces the use of expensive and complex assembly tools that are slow and relatively low yield. It is very challenging to establish a manufacturable process when the component counts are large, or high coupling efficiency is needed.
- A combination of hybrid and monolithic has proven more popular recently. Generally, a laser array on InP combines multiple sources with relative ease, and the InP array is then combined with passive optics. The two are carefully aligned and glued or epoxied in place. Compared to the fully hybrid integration, this has the benefit of a only a single alignment, albeit a difficult six axis step, but has the disadvantage that an array is much more complex than single elements, lower yield and generally lower performance.
Kaiam “optical wirebond” technology eliminates the penalty associated with fully hybrid PICs. A MEMS-based platform containing microlenses acts as the “printed circuit board”. Optical components, such as lasers, modulators, PLCs (photonics lightwave circuits) and similar single mode devices are mounted onto the MEMS assembly using conventional electronic assembly tools with loose precision. Parts can be off optimum position by tens of microns, with no optical connection to each other. However, in a subsequent “optical wirebonding step” the microlenses move to direct the optical beams and connect the components together optically. Once optimal alignment has been obtained, the microlenses are electrically locked down with integrated heaters that solder the components down permanently. The design is such that errors in the adjustment or shifts during the solder have negligible effect on the optical coupling.
The process is fully automated and can produce any densely integrated PIC, such as multi-wavelength transmitters, assemblies for coherent communication, or even consumer optics.
Kaiam is currently commercializing this technology for the 4 x 10Gb/s transceivers meeting the 40GBASE-LR4 standard in a QSFP.